AD9554 translator equivalent, multiservice line card adaptive clock translator.
Supports GR-1244 Stratum 3 stability in holdover mode Supports smooth reference switchover with virtually no
disturbance on output phase Supports Telcordia GR-253 jitter .
Quad digital phase-locked loop (DPLL) architecture with four
reference inputs (single-ended or differential) 4 × 4 cross.
The AD9554 is a low loop bandwidth clock translator that provides jitter cleanup and synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9554 generates an output clock synchronized to up to four external input .
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